instruction cycle
英 [ɪnˈstrʌkʃn ˈsaɪkl]
美 [ɪnˈstrʌkʃn ˈsaɪkl]
指令周期
双语例句
- In the field of education, teaching knowledge management is becoming the key subject in the management of classroom instruction, especially in the research of dynamic cycle.
在教育领域中，教学知识管理逐渐成为课堂教学管理尤其是有效教学研究的重要课题。 - In an SISD architecture there is a single instruction cycle; operands are fetched serially into a single processing unit before execution.
在单指令流单数据流结构中，有单一的指令周期，在执行前，单个处理机按序取操作数。 - Unlike CISC processors, RISC engines generally execute each instruction in a single clock cycle, which typically results in faster execution than on a CISC processor with the same clock speed.
不像CISC处理器，一般的RISC引擎执行在一个时钟周期，每个指令，在快上具有相同的时钟速度的CISC处理器执行一般的结果。 - In Chapter 2, we learned that the processor fetches and executes a single instruction during each machine cycle.
在第二章中，读者知道了在每个机器周期内处理器取出并执行一条指令。 - It is more efficient to design a simple instruction set that enable the execution of one instruction per clock cycle.
设计一个能够在一个时钟周期执行一条指令的简单指令系统才是更有效的。 - In other words, software interrupts always occur at the beginning of an instruction execution cycle.
换句话说，软件中断常常在指令运行周期的开始。 - Propose the run time dispatched instruction decoder and issue logic based on instruction execution cycle.
提出基于指令类型动态分配的译码器设计方案和基于指令执行周期的动态逻辑发射方案。 - The key of this design is the design of instructions state machine. Every instruction cycle includes 8 machine clock cycles, is made up of fetch instruction, decoder instruction, execute instruction, writing RAM, writing register and reading RAM etc.
本设计的关键点为指令执行状态级的设计，每个指令周期包括8个机器时钟周期，由取指、译指、执指、RAM读、寄存器写、RAM写等组成； - This article gives a detail discussion on the assembled code optimization from instruction arrangement, register division, condition selection branch and cycle structure based on the core of ARM9TDMI.
本文基于ARM9TDMI内核，从指令调整、寄存器分配、条件分支和循环结构等方面对汇编代码的优化方法进行了详细的论述。 - Reduced instruction Set Computers ( RISC) have the features such as the advantage of price performance and the shorter design cycle.
精简指令系统计算机（RISC）以其在性能价格比上所占的优势以及设计周期短等特点而得到迅速发展。 - This paper has discussed the relationship between the machine cycle and instruction execution time for superscalar RISC architecture, issuing multiple instructions in one machine cycle. Several new design features of superscalar RISC architecture with single execution unit and multiple function units have been analysed.
本文讨论超标量RISC结构中单周期发多条指令中周期和执行指令时间的相对关系，并分析了新型超标量RISC结构的实现方案，其中包括具有单个执行部件和多个执行部件的结构。 - Its instruction cycle is made up of four clock cycles. Every instruction can be executed in one instruction cycle.
它的一个指令周期由四个时钟周期组成，任何一条指令（包括跳转指令）都只需要一个指令周期就能完成。 - Simultaneous Multithreaded Processors improve the instruction throughput by allowing fetching and executing instructions from several running threads simultaneously in each clock cycle.
同时多线程处理器在每时钟周期从多个线程读取指令执行，极大地提高了指令吞吐率。 - All the 32 registers are directly connected to the Arithmetic Logic Unit ( ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle.
所有的寄存器都直接与算逻单元（ALU）相连接，使得一条指令可以在一个时钟周期内同时访问两个独立的寄存器。 - This simulation platform is an instruction level emulator, using instruction queue to simulate the pipeline structure, and analog clock is adapted to simulate the clock cycle of performing an instruction.
该仿真平台是一个指令级仿真器，采用指令队列来模拟流水线结构，并且添加了模拟时钟来模拟每个指令在执行过程中所用的时钟周期。 - To fully exploit instruction level parallelism and improve Instruction per Cycle, nowadays high-powered superscalar processors have large issue widths.
为了充分开发程序的指令级并行性以提高每周期完成指令数，当今的高性能超标量处理器普遍采用了较大的发射宽度。 - TTA architecture can achieve maximum parallel instruction set and be able to execute multiple instructions in one cycle, so the TTA architecture is very suitable for data-intensive computing tasks.
TTA架构可以实现最大限度的指令集并行，能够在一个周期内执行多条指令，因此TTA架构非常适合数据密集型的计算任务。